1. Field of the Invention
The present invention relates to the settling time of an amplifier and in particular to reducing that settling time by pre-setting a high gain node.
2. Discussion of the Related Art
FIG. 1A illustrates an exemplary amplifier 100 including an operational transconductance amplifier (OTA) 101 having a positive input terminal that receives an input signal Vin and a negative input terminal that receives a reference signal Vref. OTA 101 essentially generates a current based on the voltage differential between Vin and Vref. Note that the output of amplifier 100, i.e. Vout, is typically connected to a load. To respond to that load being heavy, light, or in transition, a feedback signal based on Vout can be provided as Vin, thereby forming a feedback loop. The reference voltage Vref is generally provided by a bandgap circuit. In one embodiment, Vref can be 1.2 V.
The output of OTA 101 drives the gate of an MOS device 102 as well as a compensation capacitor 104, which provides stability in the feedback loop. The source of MOS device 102 (in this case an NMOS device) can be connected between a voltage source VSS whereas the drain of MOS device 102 can be connected to a node 111. A current source 103 can be connected between a voltage source VDD and node 111.
Node 111 can be connected to the positive input terminal of a buffer stage 105. Voltage source VSS can be connected to the negative input terminal of buffer stage 105. The output of buffer stage 105 provides the output signal Vout.
To enable/disable amplifier 100 a bias circuit can be used. FIG. 1B illustrates amplifier 100 including such a bias circuit. In this embodiment, a low Enable signal (for example provided by an Enable pin) triggers the disabling of amplifier 100. This low Enable signal is buffered by an inverter 120, which outputs a logic high signal on a node 121 that turns on NMOS transistors 122 and 123. Therefore, the voltages at nodes 110 and 111 are pulled to ground. Notably, pulling node 110 to ground discharges capacitor 104.
The logic high signal on node 121 is also provided to the gate of PMOS transistor 124 (which implements current source 103 (FIG. 1A), thereby turning off that transistor. Therefore, there is nothing to prevent node 111 from pulling towards ground as provided by NMOS transistor 123. Thus, as shown by FIGS. 1A and 1B, when the low Enable signal puts amplifier 100 in its off state, amplifier 100 has no bias current through it.
In contrast, a high Enable signal triggers amplifier 100 to turn on. Inverter 120 inverts the high Enable signal and provides a logic zero signal to the gates of NMOS transistors 122 and 123, thereby turning off those transistors. The logic zero signal on node 121 turns on transistor 124. With transistor 124 conducting, i.e. with the current source enabled, a bias current is provided to node 111. In contrast, the voltage on node 110 is dependent on the output of OTA 101 and the effect of capacitor 104.
Thus, the voltages of nodes 110 and 111 of amplifier 100 reach equilibrium some time after amplifier 110 is enabled. The time to reach equilibrium is referred to as the settling time. Notably, because capacitor 104 slows any voltage increase on node 110, the settling time of that node takes much longer to settle than the voltages on other nodes (e.g. node 111) in amplifier 100. Thus, the settling time of node 110, i.e. the high gain node, controls the overall settling time of amplifier 100.
To reduce this settling time, capacitor 104 could be made smaller. Alternatively, the transconductance, i.e. the gm, of OTA 101 could be made higher. However, these solutions frequently increase the frequency response to the point that amplifier 100 begins to oscillate and therefore is no longer stable.
Therefore a need arises for a startup mechanism that ensures stability while decreasing the settling time of an amplifier.